Memory systems are occasionally caused to operate in a continuous burst read mode. In general, continuous burst read operation connotes a mode of operation in which a memory read request specifies a starting address from which data retrieval is to be initiated. Subsequent to the retrieval of data stored at the requested starting address, data is sequentially retrieved at successive continuous addresses. The continuous burst read operation may continue until the desired data stored in the target memory device is sensed and transferred from the memory, or until an event occurs to interrupt the otherwise continuous transfer of data from sequential addresses. Because the continuous burst read operation enables addresses and data to be prefetched in a manner that obviates latencies otherwise encountered, enhanced data transfer rates may be realized.
However, if an intervening read request, or some other event, occurs in the course of a continuous burst read operation, intervention of the ongoing continuous data read operation will be required. In this situation, the prefetched address becomes erroneous because that address no longer represents an address from which data is presently requested. Without remediation, application of the (erroneous) prefetched address can cause spurious data to appear at the memory output when an intervening address request is received that is not identical to the anticipated prefetched address. Accordingly, what is required is a technique that assures desired operation of a memory system when, in the course of a burst read operation, the received next address is different from the prefetched address.
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